IEEE SSCS Chapter Poland

🚀 Call for Student Designers: The 2026 IEEE SSCS Student Circuit Contest is LIVE!
Are you an undergraduate or graduate student looking to prove your IC design skills on a global stage? The IEEE Solid-State Circuits Society (SSCS) has officially opened the 2026 Student Circuit Contest!

This isn't your typical design project. The challenge? Build a functional integrated circuit using only a restricted list of components. It’s a game of optimization, creativity, and "doing more with less."

🏆 The Stakes
Up to 3 Winners: Receive US$2,000 toward attending a premier SSCS-sponsored conference (ISSCC, CICC, ESSCIRC, VLSI Symposium, or A-SSCC).

All Sound Submissions: Get one year of free membership in the IEEE Solid-State Circuits Society!

🛠️ The Challenge
Constraint: You must use the provided list of NMOS, PMOS, and passive components.

Goal: Maximize the number of components used while ensuring proper functionality (amplifiers must amplify, oscillators must oscillate!).

Tech: Use any IC technology available to you (must have both NMOS and PMOS).

Format: A concise 2-page IEEE-style paper including analysis and simulation results.

📅 Key Details
Deadline: May 31, 2026 (Any time zone)

Eligibility: Open to individuals or teams of two. Must be an IEEE member.

Don't miss the chance to get your work in front of the SSCS evaluation committee and fund your next big conference trip!

👉 Check the full rules and component list here: https://bit.ly/4jVCLTM
🔗 Upload your answer and fill out the submission form: https://bit.ly/40oNIG4

Już jutro (wtorek) o 16:30 hybrydowo: All-Digital PLLs: Direct Frequency Modulation. Zapraszamy zarówno zdalnie jak i na miejscu, AGH, C-2 224. Link rejestracyjny: 1ff84795-6547-4697-8491-58d29b1c263a@4fbe5e74-f50a-4a5b-8c87-f71c872ecfee" rel="ugc" target="_blank">https://events.teams.microsoft.com/event/1ff84795-6547-4697-8491-58d29b1c263a@4fbe5e74-f50a-4a5b-8c87-f71c872ecfee

Dziękujemy za liczny udział w poniedziałkowym seminarium! Było Was 41 osób na miejscu i 55 osób zdalnie. Bogdan Staszewski i Teerachot Siriburanon zaprezentowali szereg aspektów związanych z projektowaniem zaawansowanych PLLi.

Poniedziałek, 8 grudnia 2025 14:45 - 16:45 hybrydowo (AGH B-1 121 + zdalnie teams). Seminarium "Advanced topics of PLL design". Wystąpią: prof. Bogdan Staszewski i dr. Teerachot Siriburanon. Link rejestracyjny ze szczegółami poniżej. Zapraszamy! Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki AGH, MTM Mikroelektronika w Technice i Medycynie, IEEE SSCS Chapter Poland dc5d9560-08a4-4e75-bfa4-fc48e40ae929@4fbe5e74-f50a-4a5b-8c87-f71c872ecfee" rel="ugc" target="_blank">https://events.teams.microsoft.com/event/dc5d9560-08a4-4e75-bfa4-fc48e40ae929@4fbe5e74-f50a-4a5b-8c87-f71c872ecfee